There are various types of one-time programmable memory (OTPM) arrays that represent embedded non-volatile memory (NVM) technologies. In an OTPM, a write operation occurs over many write-verify cycles to achieve a large threshold shift of a memory cell. Further, depending on mismatches within an OTPM high threshold voltage (HVT) twin cell, the number of write-verify cycles may vary significantly. Each of the write operations include a write followed by a verify (i.e., read) to check if the cell is written.
In OTPM systems, the operations of the memory are performed one address at a time. For example, a single write operation may take approximately 8 milliseconds. In this situation, writing the entire memory in an OTPM system can take approximately 65 seconds (i.e., 8 banks, 256 rows, and 4 columns per bank for each write operation). Further, in OTPM systems, there is no ability to test wordline decoders of the customer array before shipping the product. Therefore, an OTPM system which reduces test time through parallel programming and adds sacrificial test input/output (IO) logic to verify the design is desired.